Serializer/deserializer (SERDES) circuits are well known in the art. These circuits may also be referred to in the art as internal transmitter/receiver (iTR) circuits.
SERDES circuits are generally incorporated into integrated circuits and operate at ultra high speeds (over 2 Gbps) and convert parallel data to serial data and serial data to parallel data. Modern day SERDES generally are capable of converting 10-bit or 20-bit parallel data into serial data and serial data to 10-bit or 20-bit parallel data.
SERDES circuits sometimes fail in the field. This occurs even though these circuits are tested during their manufacture before being released to the field. High speed imbedded SERDES circuits are generally tested during manufacturing. The tests are usually conducted at operating speed by invoking a built-in self-test (BIST) block with predetermined data patterns. For example, a first data pattern uses a 6-bit shift register. A second data pattern uses a predetermined 80-bit long pattern of mostly alternating 1s and 0s. The resulting character synchronizes the pattern back into 10-bit parallel data that is compared against expected values.
The data patterns discussed above show differences in length and spectral content. The second data pattern is longer than the first data pattern but the spectral content of the second data pattern is limited mostly to 0.5 GHz, with minor peaks at 0.25 GHz, 0.17 GHz, 0.125 GHz, 0.1 GHz, plus other lesser peaks. By comparison, a first pattern has a more complex spectral content, with multiple evenly spread peaks at 0.5 GHz and many other frequencies down to 0.083 GHz. The spectral content of the specific data sequences results in deterministic jitter or even deterministic errors. A longer sequence of 1s or 0s permits the DC level to drift closer to the rails, making it difficult to achieve an opposite level on a subsequent transition. Conversely, rapidly alternating sequences of 1s and 0s may not allow full, robust voltages to develop.
Even with a richer spectral content, specific pattern sequences may not repeat often enough to detect specific failure modes. Hence, specific pattern sequences may not occur often enough to trigger a failure mode that also exhibits a variable time-to-failure dependency due to noise or other factors. These factors will vary for difference circuits because of natural implementation differences, such as location or spatial relation to other circuitry, which in turn generates particular voltage noise sequences, not necessary correlated in time to high speed data patterns.
Hence, the prior art fixed data patterns fail to allow programming of alternate data patterns. Such alternating data patterns would be useful in the field or manufacturing tests since the integrated circuits encounter a wide variation of data patterns in the field. These data patterns encountered in the field can vary from low frequency content patterns to high frequency content patterns and various other content patterns in between. Further, some bit failures are much more difficult to capture, since their likelihood depends on system noise, which is not necessarily correlated in time with the data patterns.